Low Power Digital FIR Filter Design Using Optimized Adder and Multiplier

This paper proposes a design of low power and low delay digital finite-impulse response (FIR) filter. Nowadays, there are many portable applications requiring low power and high throughput than ever before. Thus, low power system design has become a significant performance goal. The Finite Impulse Response (FIR) Filter is the important component for designing an efficient digital signal processing system. The adders and multipliers play an important role in FIR filter while considering the power. The proposed FIR filter is designed by using Hybrid adder and Vedic multiplier from the analysis of various adders and multipliers. The Hybrid adder uses the concept of ripple carry adder and carry select adder and selects particular adder cell to perform addition operation which depends upon the carry input. The Vedic multiplier performs multiplication process in a hierarchical manner. Thus, the proposed method can minimize the dynamic power consumption and delay of the FIR filter. The experimental results show that the low pass FIR filter using proposed method achieves 10% and 1% of delay and power consumption reduction compared to conventional method. The proposed FIR Filter is simulated and synthesized using Modelsim simulator and Xilinx and power consumption results are shown by using XPower estimator tool.